module calculate

	extern	__iar_program_start
	extern	__iar_unhandled_exception

	public __my_start
	section .myvec:const(8)
__my_start
	DC16	0x8200
	DC16	__iar_program_start		;reset		-2
	DC16	0x8200
	DC16	__iar_unhandled_exception	;TRAP		-1
	DC16	0x8200
	DC16	__iar_unhandled_exception	;reserved	0
	DC16	0x8200
	DC16	__iar_unhandled_exception	;FLASH		1
	DC16	0x8200
	DC16	__iar_unhandled_exception	;reserved	2
	DC16	0x8200
	DC16	__iar_unhandled_exception	;reserved	3
	DC16	0x8200
	DC16	__iar_unhandled_exception	;AWU		4
	DC16	0x8200
	DC16	__iar_unhandled_exception	;reserved	5
	DC16	0x8200
	DC16	__iar_unhandled_exception	;extiB		6
	DC16	0x8200
	DC16	__iar_unhandled_exception	;extiD		7
	DC16	0x8200
	DC16	__iar_unhandled_exception	;exti0		8
	DC16	0x8200
	DC16	__iar_unhandled_exception	;exti1		9
	DC16	0x8200
	DC16	__iar_unhandled_exception	;exti2		10
	DC16	0x8200
	DC16	__iar_unhandled_exception	;exti3		11
	DC16	0x8200
	DC16	acc_data_ready_handler		;exti4		12
	DC16	0x8200
	DC16	__iar_unhandled_exception	;exti5		13
	DC16	0x8200
	DC16	__iar_unhandled_exception	;exti6		14
	DC16	0x8200
	DC16	__iar_unhandled_exception	;exti7		15
	DC16	0x8200
	DC16	__iar_unhandled_exception	;reserved	16
	DC16	0x8200
	DC16	__iar_unhandled_exception	;reserved	17
	DC16	0x8200
	DC16	__iar_unhandled_exception	;COMP		18
	DC16	0x8200
	DC16	__iar_unhandled_exception	;tim2 update	19
	DC16	0x8200
	DC16	__iar_unhandled_exception	;tim2 capture	20
	DC16	0x8200
	DC16	__iar_unhandled_exception	;tim3 update	21
	DC16	0x8200
	DC16	tim3_capture_handler		;tim3 capture	22
	DC16	0x8200
	DC16	__iar_unhandled_exception	;reserved	23
	DC16	0x8200
	DC16	__iar_unhandled_exception	;reserved	24
	DC16	0x8200
	DC16	tim4_update_handler		;tim4 update	25
	DC16	0x8200
	DC16	__iar_unhandled_exception	;spi		26		
	DC16	0x8200
	DC16	__iar_unhandled_exception	;uart2 tx	27
	DC16	0x8200
	DC16	__iar_unhandled_exception	;uart2 rx	28
	DC16	0x8200
	DC16	__iar_unhandled_exception	;i2c		29
	
	
	section .eeprom:const(0)
eeprom_size equ 0xA000 - 0x9EE0 
	REPT eeprom_size; 0x120
	DC8	0xFF
	ENDR

	section .mydata:data(8)
//jumpaddr
	DS16	1
	
	section .mycode:code(8)

#include "stm8s.msa"
	extern	tim3_captured
	extern	SetSpeedMode
	extern	mode
	extern	bSelected
	extern	byteToTransceive
	extern	byteReceived
	extern	byteReceivedMask
	extern	max_reset
	extern	min_reset
	;extern	tmp_word
	extern	Tim2Smcr
	;extern	PresenceFlag	
	;extern	counter
	;extern	counter2
	;extern	counter3
	extern	presence
	extern	null_slot
	extern	bitCounter
	extern	bOverdrive
	extern	LIS3DH_DataReady_Handler
	extern	bit_range
	extern	WatchdogRefresh
	public	ASM_FillFifo

//device modes	
WAIT			equ	0x80
GETCMD			equ	0x81
RESETCMD		equ	0x40
//WRITEBYTE		equ	0x02
//ENUMERATION		equ	0x03
//options bits
NO_TRANSCEIVE_BIT	equ	7
PRESENCE_BIT		equ	6
;-------------------------------------------------------------------------------
tim3_capture_handler
	clr	TIM3_SR1
	//clr	TIM2_SMCR
	btjt	mode, #NO_TRANSCEIVE_BIT, get_impuls_length	;t1uh_10
	clr	TIM2_SMCR//#######
	srl	byteToTransceive
	jrnc	test_presence_flag
	mov	TIM2_SMCR, Tim2Smcr	
test_presence_flag
	btjf	mode, #PRESENCE_BIT, get_impuls_length
	//clr	TIM3_SR1
	mov	mode, #GETCMD
	iret
get_impuls_length
	ld	A, TIM3_CCR2H
	ld	XH, A
	ld	A, TIM3_CCR2L
	ld	XL, A


	cpw	X, min_reset
	jrult	test_get_mode

	cpw	X, max_reset
	jrult	proc_reset
	mov	mode, WAIT
	clr	bOverdrive
	call	SetSpeedMode
	iret
test_get_mode	
	btjt	mode, #NO_TRANSCEIVE_BIT, test_received_bit
call_tim3_captured	
	call	tim3_captured
	iret
test_received_bit
	cpw	X, bit_range
	jrugt	shift_received_bit_mask
	ld	A, byteReceived
	or	A, byteReceivedMask
	ld	byteReceived, A
shift_received_bit_mask
	sll	byteReceivedMask
	jrc	call_tim3_captured
	iret

proc_reset
	mov	TIM2_ARRH, presence
	mov	TIM2_ARRL, presence + 1
	bset	TIM2_CR1, #0	;tim2 start
	mov	mode, #RESETCMD
	
	bset	GPIOC_ODR, #3	;CS_OFF
	clr	bSelected
	clr	TIM2_SR1
	clr	bitCounter
	clr	byteReceived
	clr	byteToTransceive
	mov	byteReceivedMask, #1
	iret
;-------------------------------------------------------------------------------
acc_data_ready_handler
	call LIS3DH_DataReady_Handler
	iret
;-------------------------------------------------------------------------------
tim4_update_handler
	call WatchdogRefresh
	iret
;-------------------------------------------------------------------------------
LAST_SAMPLE equ 5
HI_BITS_MASK equ 0xF0
LO_BITS_MASK equ 0x0F
ASM_FillFifo ; X - SampleBuffer, Y - FifoBuffer[iFifoWrite]
	push 	A
	pushw	X
	pushw	Y
	
	ld		A, (X)		;OUT_XL = X1 << 4
	and		A, #HI_BITS_MASK
	or		A, #LAST_SAMPLE
	ld		(Y), A	;last mark, X1 -> fifo
	incw	X
	incw	Y
	ld		A, (X)	;OUT_XH = X2 | X3 << 4
	ld		(Y), A	;X2, X3 -> fifo
	incw	X
	incw	Y
	ld		A, (X)	;OUT_YL = Y1 << 4
	swap	A
	and		A, #LO_BITS_MASK
	ld		(Y), A	;Y1
	incw	X
	ld		A, (X)	;OUT_YH
	and		A, #LO_BITS_MASK
	swap	A
	or		A, (Y)	;Y1 | Y2
	ld		(Y), A	;Y1, Y2 -> fifo
	incw	Y
	ld		A, (X)	;OUT_YH
	and		A, #HI_BITS_MASK
	swap	A
	ld		(Y), A	;Y3
	incw	X
	ld		A, (X)	;OUT_ZL << 4
	and		A, #HI_BITS_MASK
	or		A, (Y)	;Y3 | Z1
	ld		(Y), A	;Y3, Z1 -> fifo
	incw	X
	incw	Y
	ld		A, (X)	;Z2, Z3
	ld		(Y), A	;Z2, Z3 -> fifo
	
	popw	Y
	popw	X
	pop 	A
	ret
	end