.equ TIM2_CR1, 0x5250 + 0;   /*!< control register 1 */
.equ TIM2_CR2, 0x5250 + 1;   /*!< control register 2 */
.equ TIM2_SMCR, 0x5250 + 2;  /*!< Synchro mode control register */
.equ TIM2_ETR, 0x5250 + 3;   /*!< external trigger register */
.equ TIM2_IER, 0x5250 + 4;   /*!< interrupt enable register*/
.equ TIM2_SR1, 0x5250 + 5;   /*!< status register 1 */
.equ TIM2_SR2, 0x5250 + 6;   /*!< status register 2 */
.equ TIM2_EGR, 0x5250 + 7;   /*!< event generation register */
.equ TIM2_CCMR1, 0x5250 + 8; /*!< CC mode register 1 */
.equ TIM2_CCMR2, 0x5250 + 9; /*!< CC mode register 2 */
.equ TIM2_CCER1, 0x5250 + 10; /*!< CC enable register 1 */
.equ TIM2_CNTRH, 0x5250 + 11; /*!< counter high */
.equ TIM2_CNTRL, 0x5250 + 12; /*!< counter low */
.equ TIM2_PSCR, 0x5250 + 13; /*!< prescaler high */
.equ TIM2_ARRH, 0x5250 + 14;  /*!< auto-reload register high */
.equ TIM2_ARRL, 0x5250 + 15;  /*!< auto-reload register low */
.equ TIM2_CCR1H, 0x5250 + 16; /*!< capture/compare register 1 high */
.equ TIM2_CCR1L, 0x5250 + 17; /*!< capture/compare register 1 low */
.equ TIM2_CCR2H, 0x5250 + 18; /*!< capture/compare register 2 high */
.equ TIM2_CCR2L, 0x5250 + 19; /*!< capture/compare register 2 low */
.equ TIM2_BKR, 0x5250 + 20;   /*!< Break Register */
.equ TIM2_OISR, 0x5250 + 21;  /*!< Output idle register */

.equ TIM3_CR1, 0x5280 + 0;   /*!< control register 1 */
.equ TIM3_CR2, 0x5280 + 1;   /*!< control register 2 */
.equ TIM3_SMCR, 0x5280 + 2;  /*!< Synchro mode control register */
.equ TIM3_ETR, 0x5280 + 3;   /*!< external trigger register */
.equ TIM3_IER, 0x5280 + 4;   /*!< interrupt enable register*/
.equ TIM3_SR1, 0x5280 + 5;   /*!< status register 1 */
.equ TIM3_SR2, 0x5280 + 6;   /*!< status register 2 */
.equ TIM3_EGR, 0x5280 + 7;   /*!< event generation register */
.equ TIM3_CCMR1, 0x5280 + 8; /*!< CC mode register 1 */
.equ TIM3_CCMR2, 0x5280 + 9; /*!< CC mode register 2 */
.equ TIM3_CCER1, 0x5280 + 10; /*!< CC enable register 1 */
.equ TIM3_CNTRH, 0x5280 + 11; /*!< counter high */
.equ TIM3_CNTRL, 0x5280 + 12; /*!< counter low */
.equ TIM3_PSCR, 0x5280 + 13; /*!< prescaler high */
.equ TIM3_ARRH, 0x5280 + 14;  /*!< auto-reload register high */
.equ TIM3_ARRL, 0x5280 + 15;  /*!< auto-reload register low */
.equ TIM3_CCR1H, 0x5280 + 16; /*!< capture/compare register 1 high */
.equ TIM3_CCR1L, 0x5280 + 17; /*!< capture/compare register 1 low */
.equ TIM3_CCR2H, 0x5280 + 18; /*!< capture/compare register 2 high */
.equ TIM3_CCR2L, 0x5280 + 19; /*!< capture/compare register 2 low */
.equ TIM3_BKR, 0x5280 + 20;   /*!< Break Register */
.equ TIM3_OISR, 0x5280 + 21;  /*!< Output idle register */

.equ GPIOD_ODR, 0x500F; /*!< Output Data Register */
.equ GPIOD_IDR, 0x500F + 1; /*!< Input Data Register */
.equ GPIOD_DDR, 0x500F + 2; /*!< Data Direction Register */
.equ GPIOD_CR1, 0x500F + 3; /*!< Configuration Register 1 */
.equ GPIOD_CR2, 0x500F + 4; /*!< Configuration Register 2 */

.equ GPIOC_ODR, 0x500A; /*!< Output Data Register */
.equ GPIOC_IDR, 0x500A + 1; /*!< Input Data Register */
.equ GPIOC_DDR, 0x500A + 2; /*!< Data Direction Register */
.equ GPIOC_CR1, 0x500A + 3; /*!< Configuration Register 1 */
.equ GPIOC_CR2, 0x500A + 4; /*!< Configuration Register 2 */